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#### Motivation of Refactoring effort
A detailed technical plan can be found at [link](https://docs.google.com/document/d/15m7IbVRbQYLxFQjIVNIZT3VjYDhAqK6cjqCxVuSVDGU/edit?usp=sharing)
The overall…
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Originally reported on Google Code with ID 50
```
What steps will reproduce the problem?
1. Use a multi verilog file benchmark that employs "include"
What is the expected output? What do you see in…
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Originally reported on Google Code with ID 74
```
'A single file named parse_results.txt will be produced in the folder.'
Is this false? i'm trying to use a parse_vtr_flow.pl but the file wasn't cre…
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since 2020 there are many thousand records (~43,000) that do not contain SPPVALUE. They are NA
This is the CAMS data period.
Reached out to stockeff group. May need to reassess and reach out to C…
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this is the command I ran:
`~/vtr-verilog-to-routing/vpr/vpr k4_N4_tileable_40nm.xml xor_cipher.blif --clock_modeling route`
vpr_arch is from https://github.com/lnis-uofu/OpenFPGA/blob/master/open…
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In [`6e17394`](https://github.com/streamlined-scs/upptime/commit/6e17394342dd6f78bcbf338e661647c86ee9a784
), SAM VTR (https://seam.vtr.cl/obtenerListadoActividades?wsdl) was **down**:
- HTTP code: 0
-…
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# Convert the test runner from Perl to Python
VtR has a [`vtr_flow`](https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow) test suite runner. Currently the [scripts are…
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There seems to be an issue with running the basic usage example for `run_vtr_flow` with `-start yosys`.
#### Expected Behaviour
In the [docs](https://docs.verilogtorouting.org/en/latest/yosys/quic…
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```
In file included from /usr/ports/cad/vtr-verilog-to-routing/work/vtr-verilog-to-routing-596caca/libs/libvtrutil/test/test_small_vector.cpp:3:
/usr/ports/cad/vtr-verilog-to-routing/work/vtr-veril…
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#### Expected Behaviour
We should have no compiler warnings.
#### Current Behaviour
Some warnings in vqm2blif:
[ 50%] [BISON][VqmParser] Building parser with bison 3.8.2
/home/runner/work/vtr…