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I compiled RISC-V assembly tests and benchmarks like README,.
./emulator-freechips.rocketchip.system-DefaultConfig +verbose $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add 2>&1 | s…
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Hello,
I built a simple baremetal program [here](https://github.com/noureddine-as/riscv-baremetal-DefaultConfig), (after adding a volatile wait flag and loops); debugging using the interactive Spik…
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Hello all,
I'm trying to add JTAG debug module to the default example to use remote bitbang (debug with GDB) but when I try to build the emulator some error about **jtag_tick** shows in the terminal …
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Few tests keep failing sporadically, here a list to make sure all are addressed
Issues/PRs that may assist with this task:
- [ ] CI testing must be retry-free (avoids missing new failures) (#16469…
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Hi Mr/Ms,
There are five machine supported by riscv qemu.
sifive_e
sifive_u
spike_v1.10
spike_v1.9.1
virt
And I found that only virt support cpu number larger than 1 whic…
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An emulator of RISC-V with Linux. Should be able to execute simple binaries and debug them (`gdb`, `strace` are required at least)
Be ready to integrate along #1, i.e. in single Docker image
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1. I installed the risc-v toochain, verilator.
2. I build the verilator model by, $ make verilate DEBUG
3. Then I can see the work-ver/Variane_testharness was produced.
4. Then I compiled the hello…
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emerge --info '=dev-lang/elm-compiler-0.19.0-r1::haskell':
```
Portage 2.3.94 (python 3.6.10-final-0, default/linux/amd64/17.0/desktop/plasma, gcc-9.3.0, glibc-2.30-r5, 5.6.0-rc5 x86_64)
========…
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My intention with creating this issue is collecting/sharing information and gauging interest about running Linux on VecRiscv. From what I know, VexRiscv is still missing functionality, and it won't wo…
ghost updated
5 years ago
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The documentation of simulator-boom.system-BoomConfig tells that it is possible to run an ELF using the proxy kernel. I wrote a simple hello world program for that and compiled it using
`$RISCV/bin/r…