-
Does or will OpenFPGA Framework support Xilinx-7 series architectures like Artix-7? Because I saw things about to support Xilinx-7 series by VTR.
ghost updated
2 years ago
-
Hello! After I successfully integrated using yosys alone, I put the relevant code in openfpga and ran the entire process, and found that the error in the picture below appeared in yosys_rewrite.log.…
-
Hello! When I ran the modified task/benchmark_sweep/mac_units example of OpenFPGA, and changed the benchmark to a FIFO module written by myself or another module written by myself (the FIFO code is as…
-
After compile OpenFPGA as what is shown in the website, I am trying to verify if the tool is well compiled by run the command "python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification"…
-
I have go into the file 'k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml'
and replaced the .v file of dsp with my own design. And I checked the …
-
Hi there,
I am trying to generate act and blif files of ${OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v file. I have created counter.blif by usi…
-
I'm getting this error during first test:
"ERROR (00_counter_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_counter_MIN_ROUTE_CHAN_WIDTH
.
.
.'python3 /home/msaid/OpenFPGA/openfpga_f…
ghost updated
2 years ago
-
Sorry if this turns out to be a low level mistake on my part, but when following the [How to Compile](https://openfpga.readthedocs.io/en/latest/tutorials/getting_started/compile/) instructions on enab…
-
Hello! I recently used the k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml and k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml software of the OpenFPGA platform and gener…
-
Hello! I am very interested in this platform of OpenFPGA. Now I plan to use the K4N8 structure to generate a verilog of an EFPGA module with a size of 20*20 CLB on this platform. I would like to ask h…