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Hello! I have a question I want to ask you, that is, when synthesizing a simple verilog (code1), I found a problem as follows, I hope the teacher can give some pointers, thank you very much! !
Case 1…
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> **Describe the bug**
> A clear and concise description of what the bug is.
The CMakefile requires C++17 standard as the minimum requirement
https://github.com/os-fpga/FOEDAG/blob/…
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Is there any files allow me to check my FPGA source occupancy quickly?
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@aolofsson Looks like the OpenFPGA error is occurring because we now call `setup_tool` for every tool when `run` is initially called instead of in the relevant step directory at runtime. The OpenFPGA …
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I get the following error when I try to run `make runOpenFPGA` with the latest OpenFPGA release:
```
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_fil…
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We are currently specifying the format of the tool (cmdline, python, tcl,..). We only use this in one place within the eda step and it would seem that we can look for refdir/script keys to determine h…
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One of the new features of GHDL (which I am most excited about) is the "implicit standard version downgrade" that is achieved with `ghdl --synth`. I.e., we can take any modern and complex VHDL codebas…
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I did the following in order to run functional simulation of FPGA1212_SOFA_HD design with `and` benchmark in Icarus Verilog:
```bash
# STEP 1 ################################################
> mk…
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> **Describe the bug**
Hi, I modified and2_latch.v and added a extra reg (attached below) and took it through the OpenFPGA flow using write_full_testbench_example_script and it fails with an error "V…
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**Is your feature request related to a problem? Please describe.**
During adder implementation, if yosys has to synthesise an adder as a hard-macro and then in OpenFPGA flow, this is implemented as L…