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Hello,
We are a group of students trying to integrate a custom hardware accelerator into the PULPino. We have read the official documentation, but yet cannot find the exact method or guide on how t…
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Hi, when I execute make vcompile it compiles upto a point and gives the following error. How can I solve this issue? Thanks in advance.
```
-> Compiling apb_uart...
Copying /Software/ModelSim/ques…
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It would be nice to create some default build system. Could create a basic `make` build, or basic Modelsim/Questasim build using `vcom`. Unfortunately this varies a LOT with tool system, so it'd bas…
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Hi Marius,
I am reopening the thread again. This thread is in continuation to the old thread #23.
Please consider adding additional command as given below after the i2c_master_transmit command. …
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Hi @FrancescoConti ,
I ran successfully `cmake_configure.riscv.gcc.sh`.
Then as a next step, I am trying to run `make vcompile`
Here, I am getting below errors.
```
Scanning dependencies of ta…
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The `vsim` wrapper handling of the Vivado-generated libraries is not really optimal
The library search path, set via command line, are only available if the design is loaded from commandline`
```
…
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Hey Tristan,
This isn't an issue with GHDL as such but would be nice to get your feedback on.
Using your Xilinx-ISE compile Powershell results in the creation of separate library files for SecureI…
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Hi,
System:
MacOS with running Parallels.
Running Ubuntu 16.04 64-bit as guest OS.
Installed Modelsim 16.01 Starter Edition with 32-bit libs
Modelsim is working
compilers riscv32-unknown…
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I tested all three HDL's and only the systemverilog compiler outputs code that gives an error in QuestaSim. The error generated by questasim is as follows:
`** Error: ./Testbench_v1_types.sv (954):…
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Hello,
**The following code:**
```VHDL
entity e is
end entity;
architecture a of e is
type AT is access INTEGER;
type FT is file of INTEGER;
begin
process
variable BV : bit_vec…