Remillard VHDL-Mode issues

Remillard / VHDL-Mode

A package for Sublime Text that aids coding in the VHDL language.

MIT License

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issues

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Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?

#172 RadonicA closed 1 year ago
1
The settings file could not be opened when git cloning repo directly into Packages folder.

#171 rhasst closed 1 year ago
3
Make the is after block statement optional

#170 kalund closed 1 year ago
10
Support syntax highlight of block statement without the optional "is".

#169 kalund closed 1 year ago
2
Added record snippet

#168 martinbarez closed 1 year ago
2
VHDL beautification

#167 JYH25 closed 1 year ago
2
VHDL-Mode does not support grammar for statements: protected and protected body

#166 timothystotts opened 3 years ago
1
Version 1.8.12

#165 Remillard closed 3 years ago
0
161 Keyword `return` not scoped inside function

#164 Remillard closed 3 years ago
0
Scoping on slice assignment is confused

#163 Remillard closed 3 years ago
1
The `case?` construct syntax highlighting not working

#162 CrunchyNougat closed 3 years ago
9
Keyword `return` not scoped inside function

#161 Remillard closed 3 years ago
0
Syntax scope for subprogram file default value in error

#160 Remillard closed 4 years ago
1
Port copying from component declaration

#159 Remillard opened 4 years ago
0
Syntax in port map with cast left side

#158 Remillard closed 3 years ago
0
Strange and incorrect beautification

#157 Remillard opened 4 years ago
4
VHDL-2019 Grammar Support

#156 Remillard opened 4 years ago
0
Beautify throws exception when encountering single line procedure parameters

#155 Remillard opened 4 years ago
0
Punctuation support `<<` `>>` for VHDL-2008 fully qualified names

#154 Remillard opened 4 years ago
0
Aligning assignment to conditional

#153 Remillard opened 4 years ago
0
Reflow comment text in region

#152 Remillard opened 4 years ago
0
Parenthesis in `case` expression not scoped as punctuation

#151 Remillard opened 4 years ago
0
Pushing out version 1.8.11

#150 Remillard closed 4 years ago
0
Beautification when instantiation in block issue

#149 sverrham closed 4 years ago
6
Version 1.8.10 Release

#148 Remillard closed 4 years ago
0
Aggregate assignment syntax unsupported

#147 lenigoor opened 4 years ago
7
Releasing 1.8.9

#146 Remillard closed 4 years ago
0
Beautification of assignment on case/when lines

#145 Remillard closed 4 years ago
3
Syntax of Label and Process on separate lines

#144 Remillard opened 5 years ago
1
Syntax scope error in entity interface list with type casted defaults

#143 Remillard closed 4 years ago
1
add vhdl template feature

#142 jozwa closed 5 years ago
1
Beautification Indent of Nested WHEN / IF statements

#141 jozwa closed 4 years ago
6
Version 1.8.8 Release

#140 Remillard closed 5 years ago
0
Finishing generic type support

#139 Remillard closed 5 years ago
0
Support Generic Type

#138 Remillard closed 5 years ago
2
Fixed #104 Finally -- Woohoo!

#137 Remillard closed 5 years ago
0
Add GitHub issue and pull request templates

#136 dominiksalvet closed 5 years ago
3
Everything block related addressed

#135 Remillard closed 5 years ago
0
VHDL-2008 block commenting breaks beautification

#134 Remillard closed 5 years ago
0
"block" syntax not recognized by syntax highlighting or beautification

#133 rolpks closed 5 years ago
10
Version 1.8.5

#132 Remillard closed 5 years ago
0
Fixed closing stack deque error in issue #130

#131 Remillard closed 5 years ago
0
Create testbench crashes when entity has a generic

#130 Remillard closed 5 years ago
1
Merging fixes into the master branch

#129 Remillard closed 5 years ago
0
Operand overload

#128 ni-maxkoehler closed 5 years ago
5
Keywords in interface declaration

#127 Remillard closed 5 years ago
2
More Assignment Alignment Issues

#126 Remillard closed 5 years ago
1
Assignment continuation lines behavior

#125 Remillard closed 5 years ago
1
Assert Scope Error

#124 Remillard closed 5 years ago
3
Release 1.8.2

#123 Remillard closed 5 years ago
0