-
Hi, I'm trying to run the following (simple code):
```python
from migen import *
from migen.fhdl import verilog
m = Module()
counter = Signal(24)
led1 = Signal()
m.comb += led1.eq(counter[…
-
**Issue by [mithro](https://github.com/mithro)**
_Tuesday Dec 18, 2018 at 00:37 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/10_
----
A huge number of issues in the old migen …
-
## Steps to reproduce the issue
I am using proprietary files so I can't include all files to reproduce the problem.
Attached is [SnowWhiteI.zip](https://github.com/YosysHQ/yosys/files/2922114/Snow…
-
The replace signal of SyncFIFO is not properly initialized during a reset making it incompatible with ASIC implementation. Given following code:
```python
from migen.genlib.fifo import SyncFIFO
fro…
-
It seems that we have both a `litex.build` and a `migen.build` now. Should we be trying to merge them?
-
- On Sayma RTM v1.0 there are 10 unused diff pairs on the RTM connector. On the AMC these connect to: GTP8RX-GTP10RX and SYNCOUT{1,2}1
- On Sayma RTM v2.0 we will completely remove (i.e. not just DNP…
-
**Issue by [dlharmon](https://github.com/dlharmon)**
_Sunday Sep 22, 2019 at 20:56 GMT_
_Originally opened as https://github.com/m-labs/nmigen/pull/227_
----
Related: #212
This tags the first r…
-
```
Traceback (most recent call last):
File "./make.py", line 164, in
main()
File "./make.py", line 123, in main
soc = get_soc(args, platform)
File "./make.py", line 57, in get_so…
-
Hi, I'm trying to wrap my head around the LiteX/Migen world because I want to get LiteScope running on my Lattice HX8K board. However, this is unfortunately turning out to be a rather frustrating expe…
-
```py
s.clock_domains.cd_spi = ClockDomain()
s.active = Signal()
s.bitcount = Signal(24)
s.cmd = Signal(8)
s.addr = Signal(24)
s.comb += [
…