-
Looking at `SDC_analysis/and2_fpga_top_analysis.sdc` file, there seem to be weird top/left/right/bottom edge components that do not seem to exist in the design.
For instance, I see this error with …
-
**Is your feature request related to a problem? Please describe.**
Move doc building to gh-pages than readthedocs, because
1. reduces the dependencies on other services
2. gh-pages are more custo…
-
I have been trying to create a .act file for a .blif file of my own, but it shows the following error:
Line 10: Cannot find the model for subcircuit NOT.
Reading network from file has failed.
/ho…
-
I just noticed that the renamed openfpga_setup.py file now sets 'copy' to false. However, copying the files was necessary to move the OpenFPGA script template into the working directory. Changing 'cop…
-
When multiple vpr_arch.xml files are specified, corresponding to a specific timing corner delay data in it, then symbiflow should run the flow considering CORNER as an input and based on this input, i…
-
I am running Ubuntu 18.04 and installed OpenFPGA and compiled it. When I run the following command to confirm that I compiled correctly, I get the following error:
python3 openfpga_flow/scripts/run…
-
I noticed multiple issues in the current task run flow. It looks to have various hard-codings or assumptions.
My intention is to write a testcase to run yosys by invoking synth_quicklogic and here ar…
-
With the recent work to use parametric style verilog, I believe there is a stronger case for https://github.com/RAPcores/rapcores/pull/154. The root issue of that approach is that most data was made r…
-
line94:
"-Wcast-allign" ==>"-Wcast-align" in line 101?
-
I'm trying to use a rr graph generated using the VPR version currently used in OpenFPGA project (can't establish exact VPR revision, the OpenFPGA revision is `a9f91513`) with the upstream VPR. I'm enc…