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error
CL/opencl.h: No such file or directory
solution
```
file: papaa-opencl-master/opencl-src/alexnet-altera/Makefile
INC_DIRS += /home/ubuntu/altera/16.0/hld/host/include
```
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Instructions are not working.
https://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign#3
mkdir atlas
cd atlas
wget https://github.com/dwesterg/atlas-soc-ghrd/tarball/master -…
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Hey, i have never use a FPGA borad, i will try the prodject on a smalelr device to understund more and mabye in the futurce buy and bigger board.
I looked up Altera MAX II EPM240. and under stund th…
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We think @arya1080 forgot to commit the updated Qsys files; error log below:
Error (12006): Node instance "dac_gain" instantiates undefined entity "qsys_system_dac_gain". Make sure that the requir…
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Clang 14.0.0
I have a macro like this:
```c
#define GET_ARG(...) do { get_arg_impl(__VA_ARGS__); } while(false)
```
clang-tidy suggests adding `#pragma unroll` even though that doesn't make sen…
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Hi everyone,
I am trying to simulate a design containing some Altera IPs but for all of the IPs GHDL give me a warning `"instance "IP" of component "IP" is not bound"`. So, I just created a PLL and…
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What is required to be able to use Yosys with ISE for Spartan-6 and Spartan-3 devices?
I assume the following things are needed;
1) [ ] Description of the black boxes like SERDES and such,
2) […
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Hi,
I was looking at your whole code, You are using some components in your design that I cannot find their source code. Would you please give me a hint to find them.
dcfifo ==> in all FIFO mod…
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This is what I get trying to create a virtual environment:
```console
$ uv venv
× Could not detect either glibc version nor musl libc version, at least one of which is required
```
Someon…
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### What happened?
Ao carregar algum anexo no FileUpload o campo Money altera a mascara mudando um número da esquerda para a direita da virgula. Ex. Valor 55,44 após carregar um anexo fica 5,544
##…