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I just tried if I can reproduce https://github.com/enjoy-digital/litex/pull/1259 on BlackParrot.
Unfortunately using BlackParrot and the Arty board the `demo.bin` gets stuck on lift-off even if `-flt…
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Hello,
I understand that Arty A7 is supported, I want to confirm if Arty S7 need something extra to work.
I follow the build instructions and when loading the gateware on Arty S7 I am getting the …
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Repro:
```python3
from nmigen import *
from nmigen_boards.arty_a7 import ArtyA7_35Platform
# Resource("eth_clk50", 0, Pins("G18", dir="o"),
# Clock(50e6), Attrs(IOSTANDARD="LVCMOS33"…
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Hello, thank you very much sharing your valuable materials. I have some experience using Vivado HLS but I am still a slow learner for Hardware/FPGA design.
I am trying to run these Verilog files wi…
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I'm investigating an issue where a specific write-write-read sequence returns an incorrect result.
My LiteDRAM core is configured for Arty A7 with a 32-bit wishbone port.
I was able to reproduce th…
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Do you want access to the Fossil repository? Maybe this could be kept on a branch, of course that is up to you what you prefer! :-)
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According to some forum comments, I check out FreeRTOS branch but find nothing about FreeRTOS. And under V1_0FreeRTOS branch, I cannot pass the compilation.
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Hi,
I was looking through usb/usb_dfu_ctrl_ep.v to determin why I am not able to boot the application for the logicbone target.
In the following section:
```
// The DFU specification suggests …
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Hello,
I'm using poll in conjunction with timerfds and the `POLLIN` event to schedule actions at different rates. I'm finding that when `CONFIG_SCHED_TICKLESS` is used, poll is returning with only…
g2gps updated
2 months ago
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Just received the Arty A7: Artix-7 and was keen to get started but failed at the first hurdle !
After cloning, make install fails with:
`make: *** No rule to make target 'install'. Stop.`
F…