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I've been trying to generate the bitstream targeting VCU118 for benchmark purposes.
To generate the bitstream, [the wiki](https://github.com/fpgasystems/fpga-network-stack/wiki/Getting-Started-Guid…
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### Describe the bug
Errors while trying to convert CUDA code from Open3D to SYCL. Happens for any CUDA file.
The errors are about unknown compiler options (warning control options that clang and g+…
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Win11, Winpython64-3.12.4.1, Spyder 5.5.5, xrt-1.6.0
Run example in xrt-master\examples\withRaycing\06_AnalyzerBent1D\01B_BentTT.py
When set useTT is True, the following error message appears:
![…
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I am trying to buuild `zcu102_pl_ddr_stream` platform but I am getting following error, while I can make `zcu102_base` platform without any problem. I wondering what can be the cause of the problem.
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Update silicon target to use bsg_time() when it's available. It can probably supported using the fpga on the board.
vb000 updated
4 years ago
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Have you tested Lizard on an FPGA at all? What type of resource usage do you think it would use? (How big is the number of gates in the ASIC flow?)
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### Describe the bug
Affected tests:
```
********************
Unexpectedly Passed Tests (14):
SYCL :: Matrix/SPVCooperativeMatrix/element_wise_abc.cpp
SYCL :: Matrix/SPVCooperativeMatrix/ele…
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There are better chips available for future versions of PSLab. One recommendation is LPC43S70FET256: 32-bit ARM Cortex-M4 + 2 x M0 MCU; 282 kB SRAM; Ethernet; two HS USBs; 80 Msps 12-bit ADC; configur…
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### Test point name
[chip_sw_spi_device_pass_through_flash_model](https://github.com/lowRISC/opentitan/blob/07ece748876891301ac6eaba354541d4a57d39c6/hw/top_earlgrey/data/chip_testplan.hjson#L181)
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Hi all,
The HWPE behavior between simulation and FPGA is different. I've tried it with pulp_soc v2.1.0, v3.0.0 and v3.0.1. They all show the same problematic behavior so far.
**INFO:** I'm using…