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Demo proje dosyalarını henüz repository'e eklemedim. Fusesoc konusunda localde birkaç problem yaşıyorum. Onları düzelttikten sonra buraya o şekliyle ekleyeyim projeyi.
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## Observed Behavior
As the attached log file shows, [fusesoc.log](https://github.com/user-attachments/files/16245198/fusesoc.log), Verilator compile of the Cheri Ibex fails if the RV32E paramete…
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The flow should include:
- Building of reference ELF files
- Running of ELF file simulation with FuseSoC
- Reporting of results
@wallento is also going to provide TAP reporting in FuseSoC. If it's do…
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This will allow us to portably build the tests for different verilog simulators so that people can more easily use the tests.
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Is it possible to extract the control signals of the processor corresponding to the RTL code of the or1200 processsor for a given set of instructions ?
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Hello,
I cloned repository
`https://github.com/olofk/de0_nano_ipxact/tree/master`
which contains a core-file with CAPI-version 1 and tried to migrate it to version 2 with following
`fuseso…
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### Description / Steps to reproduce the issue
There is a problem with the code generated by verilator that it can not use certain unix constructs,
1. install verilator:p, rust:p, python-pip:p
2. d…
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Im using ubuntu 18.04 in WLS. When running the command : sudo fusesoc run --target=sim veerwolf, I get the following error:
INFO: Generating ::veerwolf-veer_eh1_default_config:0.7.5
Traceback (mos…
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Since this repository utilizes FuseSoC, how to find a submodule is less obvious compared to those using Makefile. For example, ` corescore/rtl/corescore_tinyfpga_bx.v` initializes the module `axis_asy…