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For whatever reason I manage to tickle the iCE40 BRAM startup erratum about every three years.
In this case, I'm evaluating Amaranth and brought up the iCE40 PLL for the first time. I wrote somethi…
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There are some debug leftovers in the target file: https://github.com/timvideos/litex-buildenv/blob/master/targets/ice40_hx8k_b_evn/base.py#L82.
This one needs testing on HW and (probably) some mor…
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Hello, when running
`apio verify --board icestick`
I get the following error.
iverilog -o hardware.out -D VCD_OUTPUT= -D NO_ICE40_DEFAULT_ASSIGNMENTS "C:\Users\jemo0\.apio\packages\tools-os…
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Hello Adrian, this is a great new release/upgrade.
I was wondering when you will release your SNAPPY2020 cartridge shown by Robin on youtube?
Or is there some place we can see the progress?
Many t…
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Apologies if this is the wrong place to post this I'm pretty new to icestudio and FPGAs in general.
Im trying to create a bi-directional switch on an I2C data line but I can't seem to get it to bui…
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Hey, despite Symbiflow mentioning ice40 support based on icestorm being supported, there seems to be no mention of it in this repo.
Is this anywhere on the radar?
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This includes:
- The LimeSDR board https://github.com/myriadrf/Novena-RF
- MadHacker's iCE40 FPGA board https://www.jamiecraig.com/novena-ice40-add-on/
- The novena guide at https://github.com/bn…
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in #738 one of the CI run failed on ice40 tests (https://source.cloud.google.com/results/invocations/df596a9c-9100-4b5f-b727-4300172a64a1/targets/foss-fpga-tools%2Fsymbiflow-arch-defs%2Fpresubmit%2Fic…
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Hello there,
I am trying to get timing data for modules without assigning/requiring IO placement.
For ECP5 out of context has worked great. Can the same be done for iCE40?
I tried `nextpnr-ic…
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The iCE40 UP5K has DSP blocks. [They are described here](http://www.clifford.at/icestorm/ultraplus.html).
We should describe them in xml / verilog.