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Need at least an `alwayslink=True` on the kernel link target and pointing somewhere else as the `YOSYS_DATDIR` in the defines. Been using out-of-tree binaries thus far, but we should be able to resolv…
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Hello,
I’m a bit confusing about the source files organisation.
Current:
```
Agilack/eCow-logic
├── pico-ice40-1k
│ ├── hdl-example-k2000
│ ├── hdl-example-spi
│ ├── hdl-example-vga
│ ├── h…
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I tried to open existing json file generated for picosoc, bels, nets etc seems to load from json, but nothing is highlighted in gui (clicking on fpga structure selects appropriate bel for example, but…
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This has been an issue I've discussed with @eddiehung for a while, but I want to file it publicly so people can submit testcases for us to work through.
Essentially, the problem is that ABC9 - whic…
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The current VexRISCV configuration works well on big FPGAs like the Artix-7 and Spartan 6 but is too big for the tiny iCE40 based devices.
It would be good to add a variant which works well on the …
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There are some debug leftovers in the target file: https://github.com/timvideos/litex-buildenv/blob/master/targets/ice40_hx8k_b_evn/base.py#L82.
This one needs testing on HW and (probably) some mor…
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I am trying to run your ice40-playground memtest project to test Hyperram on a Blackice MX board.
I successfully ran it on an iCEBreaker board. My Pmod is the single Hyperram chip version.
I cha…
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As the arachne-pnr github says: Arachne-pnr is not maintained anymore; use nextpnr instead, which is a complete functional replacement with major improvements.
The commands to use nextpnr-ice40 wit…
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I'm hitting
nextpnr-ice40 -q --lp384 --package cm36 --pcf tinyfpga_bx.pcf --json servant_1.0.2.json --asc servant_1.0.2_next.asc
terminate called after throwing an instance of 'nextpnr_ic…
olofk updated
4 years ago
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```
ctx.addClock("clk_out_a", 100)
ctx.addClock("clk_out_b", 12)
```
```
nextpnr-ice40 --pre-pack clocks.py
```