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## Issue Description
`memory_libmap` pass in Yosys 0.18 and newer would synthesize LUTRAMs unsupported by nextpnr including:
- RAMS32 (manually instantiated)
- RAMD32 (manually instantiated)
- R…
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We plan to write some initial support for this FMC to have it ready when prototypes arrive.
The idea is to have quite versatile AWG in the classical sense, I mean that the user defines the samples an…
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Many emulators support ways to debug their guests using more suitable tools - GDB, LLDB, EDB, WinDbg, IDA Pro, etc.
Implementing something like gdbstub, just like QEMU does this, will allow remote …
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Hi all,
As far as I can see from the Chisel files the L1 D cache replacement policy is defined to be Random replacement. The Pseudo LRU policies are defined just for higher level caches and my att…
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```
[big-vl@ho qemu]$ sudo build/qemu-system-xtensa -machine help
[sudo] password for big-vl:
==207161==WARNING: ASan doesn't fully support makecontext/swapcontext functions and may produce false …
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## Issue Description
As discovered in https://github.com/openXC7/nextpnr-xilinx/issues/20#issuecomment-1938392685, nextpnr packer was checking the wrong INIT parameter without the underscore and pr…
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Hello,
I am trying to port the FGPU core in a KC705 plattform and exclude the floating point units (FPU). Could you please help me to figure out ho to exclude FPU ?
Thanks in advance for your ti…
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I am trying to connect a custom accelerator to the cva6 axi bus. This accelerator will have an AXI slave port for configuration and an AXI master port for reading and writing data directly off main me…
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# Question
What happens in the gatware when there is a delay/jitter on the reference clock provided to the KC705?
## Category: Gateware
## Description
This isn't a bug, but more of a question …