-
Hi.
I'm trying to run the PCIe demo, the bitstream in https://github.com/sipeed/TangMega-138KPro-example/blob/main/pcie/PCIe2.0_dma_demo/pcie_dma_demo.gar , but the board is not recognized as PCIe …
-
Hi,
I am trying to build rocket chip for terasic de2115. There are some issues which i think some one with more knowledge on rocket support for de2115 could clarify more and suggest fixes.
I fi…
-
Hi,
I just run a test on Windows 10, filtering only multichannel devices listed using `if (MultiChannel.usePortAudio()) {` All MME drivers are working properly. However all ASIO and WDM-KS drivers …
-
As far as I understand, the [config.json](https://github.com/hanchenye/scalehls/blob/master/samples/polybench/config.json) file has information about the target FPGA (number of DSPs etc) that are used…
-
Hi,
I've started working with this tool. I tried to convert a simple xgboost tree into VHDL. Conifer is creating the files without a problem, however when I try to import them in Vivado it's a mes…
-
I am attempting to build the torus kernel for the LINPACK benchmark, but the build errors out in the link stage due to an invalid port mapping. I'm not sure I understand why this issue is occuring, bu…
-
Hello, we are trying to implement pulpino on Arty a7 35t but it is showing the following error. Can anyone please help us with this?
``````
source pulpino.tcl -notrace
CRITICAL WARNING: [Board 49…
-
Author: **Author 1**, **Author 2**, **Author 3**, ...
**Keywords:**
Community resilience, vulnerability, interaction of physical and social vulnerabilities, demographics, human well-being, environm…
-
During the TSC meeting on Oct 15 it was decided that we are going to collect some draft use cases for `#pragmas` as a first step to work on syntax and functionality. Please, add you use case as a comm…
-
Hello,
Can anybody point me to a stable branch and commit for what concerns the RTL of the nv_small configuration? Please let me know if you were able to compile and synthesize the RTL sources in V…