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Hi,
I got the following output when reading the attached design checkpoint
>==============================================================================
== Reading DCP: soc…
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Could you please merge the `lut0_support` branch into main? It is solving a Segmentation Fault issue for some designs see Xilinx/RapidWright#853
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Can we bring in fewer submodules in the CI when they are not needed?
Perhaps using this approach:
```
git submodule init
```
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Is there some api to use vivado in rapidwright? such as generate bit after dcp generated!
Thanks so much!
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How to use the outmux(a|b|c|d) while create a cell?
Thanks so much!
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==============================================================================
== SLRCrosserGenerator ==
========================================…
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How to transfer the file to dcp file?
the target device is xcvu3p-ffvc1517-1-i;
the nets' key are source tile.wire and sink tile.wire;
the nets' values are tile.dst_wire.src_wire;
the ins in cells…
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How to transfer xdl to dcp file?
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How to generate the device database rather than download the data?
Thanks!
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I got the following warnings when reading a design checkpoint (attached) generated from another flow (that was created using ModuleInst)
>...WARNING: Hierarchy information reference to non-existent…