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rachelselinar
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DREAMPlaceFPGA
An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
BSD 3-Clause "New" or "Revised" License
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IndexError placing design with DSP
#31
eddieh-xlnx
opened
2 weeks ago
0
KeyError placing design with RAMB18
#30
eddieh-xlnx
opened
2 weeks ago
0
[AMD Internship - Zhili Xiong] Native FPGA Interchange and Shape Support
#29
clavin-xlnx
opened
1 month ago
0
Update requirements.txt
#28
zhilix
closed
1 month ago
0
Fccm 24
#27
zhilix
closed
7 months ago
0
"RuntimeError: radix_sort: failed on 1st step: cudaErrorInvalidDevice: invalid device ordinal" for GPUs with compute capability 8.6 and higher
#26
rachelselinar
opened
7 months ago
0
Runtime Error: cudaErrorInvalidDevice
#25
keyplay
closed
8 months ago
2
Lut0 support
#24
rachelselinar
closed
1 year ago
0
Segmentation Fault on GNL Designs
#23
clavin-xlnx
closed
1 year ago
1
NonLinearPlaceFPGA.dump() not defined
#22
hailiangh
opened
1 year ago
1
add the docker support
#21
Ethan0Jiang
closed
1 year ago
0
Placement Runtime in DREAMPlaceFPGA
#20
Yk2Zcc
closed
1 year ago
5
Fix IF2bookshelf port maps
#19
zhilix
closed
7 months ago
0
Fix divide by zero caused by 1-pin nets in LG (CUDA)
#18
rachelselinar
closed
1 year ago
1
Fix IF2bookshelf for bussed nets
#17
zhilix
closed
1 year ago
0
IndexError in place_io.py
#16
clavin-xlnx
closed
1 year ago
2
Interchange to Bookshelf converter doesn't properly handle bussed nets
#15
clavin-xlnx
opened
1 year ago
3
Move LUT occupying entire BLE to 6LUT location instead of 5LUT
#14
rachelselinar
closed
1 year ago
5
move 5LUT to 6LUT
#13
zhilix
closed
1 year ago
1
Error when running program with "detailed_place_flag" : 1
#12
magic3007
closed
1 year ago
1
Error running ISPD2016 FPGA12 benchmark
#11
magic3007
closed
1 year ago
1
fix LUT6_2 and RST
#10
zhilix
closed
1 year ago
1
[IFWriter] SRST{1,2} site pins on VCC net even if no FFs in SLICE
#9
eddieh-xlnx
closed
1 year ago
1
Handle LUT6_2 in IFWriter
#8
rachelselinar
closed
1 year ago
1
[IFWriter] Both LUT6_2/LUT{5,6} cells are mapped to ?6LUT bel
#7
eddieh-xlnx
closed
1 year ago
1
Missing Python Requirement
#6
clavin-xlnx
closed
1 year ago
1
Always one instance being placed to "1 0 15"
#5
zhilix
closed
1 year ago
1
Interchange format
#4
zhilix
closed
1 year ago
0
Interchange format(IF) support
#3
zhilix
closed
1 year ago
1
Support `torch==1.13`
#2
makslevental
closed
2 years ago
0
The "make" errors with different pytorch versions
#1
liumengbjut
closed
2 years ago
1