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Can someone help me understand this snippet of code from `dec_tlu_ctl.sv`? I am not familiar with the naming convention of the SweRV core either, so I would also appreciate if someone can enlighten me…
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Hi,
I am using following doc to build tool-chain
https://riscv.org/wp-content/uploads/2015/02/riscv-software-stack-tutorial-hpca2015.pdf
at slide 18, it is mentioned to Generate RV32 code.
Tryi…
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// file "decode" is human readable file that has all of the instruction decodes defined and is part of git repo
// modify this file as needed
// to generate all the equations below from "decode" e…
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================================================================================
INFO: Wrote dependency graph to /home/nicolast0604/swervolf/build/swervolf_0.7.3/nexys_a7-vivado/swervolf_0.7.3.deps-a…
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For testing FPU unit + more
mmhus updated
3 years ago
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As discussed offline, there might be some inconsistencies of a manually built Yosys+UHDM vs. the Conda builds used in
https://github.com/SymbiFlow/sv-tests CIs.
There are some of these tests that…
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I implemented SweRV_EH1 on a Zedboard fpga. I am trying to use openOCD and Jtag Arm-USB-Tiny_H to download code to the board as instructed in the README. I have checked the physical connection and ma…
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Hi,
Any advice how to run these test on verilog model of a processor (with no OS)?
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I have your design running in nexys A7 with an EL2 core.
When I do a sequence of writes to an I/O port, such as GPIO, and my code is running in ICCM, the writes are lost, except for the last one. …
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# 总结
- https://github.com/cisen/blog/issues/760
- https://github.com/tock/tock
- https://github.com/cisen/sourcecode-tock-01
- https://github.com/oxidecomputer/tockilator
- demo: https://github.c…
cisen updated
2 years ago