chipsalliance Cores-SweRV_fpga issues - Githubissues

chipsalliance / Cores-SweRV_fpga

Apache License 2.0

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issues

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Mark this repo as deprecated or remove it

#8 olofk opened 1 year ago
0
Routing issue when implement SweRV Core in Zedboard

#7 kingstone1927 opened 3 years ago
1
Debug Module did not become active. dmcontrol=0x0

#6 kingstone1927 opened 3 years ago
1
Can not debug with openocd

#5 zhuzhizhan closed 3 years ago
0
Placement error

#4 monniaux opened 3 years ago
3
can't receive UART data from hello.c code

#3 damiencarrier opened 4 years ago
1
Cannot communicate through OpenOCD with Nexys A7

#2 monniaux opened 4 years ago
13
Added SweRV JTAG pinout to README

#1 JanMatCodasip opened 4 years ago
0