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**Issue by [dlharmon](https://github.com/dlharmon)**
_Sunday Sep 22, 2019 at 20:56 GMT_
_Originally opened as https://github.com/m-labs/nmigen/pull/227_
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Related: #212
This tags the first r…
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- On Sayma RTM v1.0 there are 10 unused diff pairs on the RTM connector. On the AMC these connect to: GTP8RX-GTP10RX and SYNCOUT{1,2}1
- On Sayma RTM v2.0 we will completely remove (i.e. not just DNP…
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Hi, I'm trying to wrap my head around the LiteX/Migen world because I want to get LiteScope running on my Lattice HX8K board. However, this is unfortunately turning out to be a rather frustrating expe…
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## Actual Behavior
The following Verilog module:
```
/* Machine-generated using Migen */
module top(
input clk16,
input usb_d_p,
input usb_d_n,
output usb_pullup,
output user_led
);…
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This seems possibly important?
```patch
--- third_party/litex/litex/build/xilinx/common.py 2018-10-03 15:56:19.937855898 -0700
+++ third_party/migen/migen/build/xilinx/common.py 2018-10…
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```py
s.clock_domains.cd_spi = ClockDomain()
s.active = Signal()
s.bitcount = Signal(24)
s.cmd = Signal(8)
s.addr = Signal(24)
s.comb += [
…
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Some team from US lab which I cannot disclose right now (their procurement would not like it), asked us to build universal, low cost FMC carrier with specification:
- designed using KICAD, of course …
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FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations wi…
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Author Name: **Patrick Stewart**
Original Redmine Issue: 1363 from https://www.veripool.org
Original Assignee: Patrick Stewart
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I've added support for building with CMake (the verilated o…
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I tried to build ov_ftdi. I gave a 'make' in the folder 'ov_ftdi/software/fpga/ov3' and got the below error
Could you let me know how can I remove the below error? I am not sure if I have an updated…