-
**Describe the bug**
Hi Ganesh/XiFan:
Just want to give you an update on the verification that Rakesh is running and we notice of the following to see if this can be taken care of in OpenFPGA:
…
-
Hi
https://github.com/OpenFPGA-ICE looks quite similar to your github,
and uses the same icesprog.
How the 2 boards are related ?
-
I used the exactly same setup as the IceBreaker ICE40 dev board with 64x64 panel. I was able to build rgb_panel project with Pattern mode successfully, but nothing showed up on the panel. it's pure bl…
-
1->I have successfully compiled the OpenFPGA project.
I want to access OpenFPGA Shell.
Do i need to setup environment variable to access this shell globally..?
-
```
Traceback (most recent call last):
File "/opt/openfpga/vtr/bin/python/create_ioplace.py", line 151, in
main()
File "/opt/openfpga/vtr/bin/python/create_ioplace.py", line 115, in main
…
-
Hello,
im now working on the bitstream generation for the new custom block, for example blackbox.
According to your paper TGA+19, i generate a physical mode and an operating mode, both have the mod…
-
Hi,
this time i wrote a new custom block called "blackbox", which includes an adder and a flipflop module in the vpr-arch, and want to link it with the circuit model in the openfppa-arch. Unfortuna…
-
Hi,
i got a new problem.
After i use commend "python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain" to generate the verilog code, i find the module in t…
-
Hi, I tried to run openfpga shell by using `run_fpga_task.py`. When the flow I chose was `vpr_blif`, the result was successful, but the flow I chose was` yosys_vpr`, the result was error. This is repo…
-
Hello,
sorry for the disturb again. I kinda have a new problem.
I made a few changes in the k6_frac_N10_adder_chain_40nm_openfpga.xml. For example, i wrote a 8-to-1 multiplexer and used it in the…