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In order to allow easy polling the AXI register shouldn't just [store](https://github.com/robertguetzkow/speck-cipher-hardware/blob/c99e0120e00d515710e1c9de63456e59348f62dc/vhdl/interface/Speck_AXI_v2…
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Hi, everyone.
Now, I have been developing CNN of unique design.
My designed architecture is:
The input image is 60 x 60 x 1 (x, y, c).
The output is 3 classes.
The hidden layer is CNN gen…
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Hi
Change 3e098f567af0a442ae9f3a41b0fcb90f2092daed modifies the behaviour of the check_stream/check_axi_stream function.
The check functions call the pop function one by one. The command queue to …
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Description: Combinational paths exist from data_rvalid_i and data_err_i to data_req_o and from instr_rvalid_i to instr_req_o. Such paths can potentially limit the achievable performance in systems th…
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I'm considering updating the picorv32 core for the FuseSoC standard library, but it would be great to have a tagged release that I can use
olofk updated
5 years ago
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I'm referring to this file:
https://github.com/raspberrypi/documentation/blob/JamesH65-mailbox_docs/configuration/mailboxes/propertiesARM-VC.md
First, it seems the 0x00038045 and 0x00030045 tags…
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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**What is the current behavior?**
The MMIO/ExtBus size parameter specified here:
https://git…
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Sometimes, when try to use two way transfer I get timeout error (in receive part). Also, I see that data correctly send out from DMA, but in some causes incorrect received (if set false on wait).
[t…
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I have an issue with building the boom-template verisim project, the make process fails and doesn't generate the binary target. I am new to this problem so perhaps I am just doing something wrong. It …
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The RTL code generated for an example register specification ( [sample.xls](https://github.com/taichi-ishitani/rggen/blob/master/sample/sample.xls) ) crashes Quartus.
Tested with Quartus 18.0.0 Sta…