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int this wiki "https://github.com/openrisc/community-wiki/blob/master/Ubuntu_VirtualBox-image_updates_and_information.mw" i find the image (ftp://ocuser:ocuser@openrisc.opencores.org/virtualbox-image/…
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Greetings,
I'm currently trying to get into SpinalHDL,
and to use XSim simulation on Windows.
In the test project's `Config.scala` I changed the `def sim = SimConfig.withConfig(spinal).withFst…
oletf updated
9 months ago
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Hello hello! First of all great work on cocotb. My mental sanity is thanking you for making me not write verilog test benches.
I'm setting up a project in which I want to have test benches for each…
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Hi Ben,
This may be a beginner question but I have tried running the test suite through intellij and also through command line. I have a modern linux machine but running millions of tests is taking…
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For a new project, Verilator build phase is taking too long (more than 40 minutes which is 40 times longer than what I see on even driven simulators). This is quite unusual and contrasting with my pr…
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Hello,
I'm moving away from xsim to verilator and have a big library of GTKWave `.gtkw` files for viewing traces of all my simulations. When I generate trace files both programs emit different scop…
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I follow the [docs](https://cfu-playground.readthedocs.io/en/latest/setup-guide.html) in my VM ubuntu 20.04. It seems that everything works well. After I type `make renode` in CFU-Playground/proj/exam…
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Hi,
When I tried to run the script run_ipgen.sh, I found out that this script failed, and showed the following errors in the log:
![image](https://user-images.githubusercontent.com/12812787/1564…
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So according to the VPI book, the most effective way to drive some multi bit register with value using **vpi_put_value** is using the format of **vpiVectorVal** and its corresponding **aval** and **bv…
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You should be able to see the problem with the following testcase code. Copying this code into a buffer and updating the AUTOs, you should see that no declaration is created for the "a" output. If y…