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I followed Vitis [Getting Started Tutorial](https://github.com/Xilinx/Vitis-Tutorials/blob/2023.1/Getting_Started/Vitis/Part4-data_center.md#building-and-running-on-alveo-u250-data-center-accelerator-…
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The newest deployment package `xilinx-u280-gen3x16-xdma_2023.1_2023_0507_2220-all.deb.tar.gz` is missing dependent xilinx-cmc-u280, which will cause an error during installation. If you are a Xilinx e…
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Greetings,
I am using Vivado 2021.2 and trying to port the platform to Alveo U280. When building the hardware:
```
[Sat Feb 24 16:36:44 2024] Launched box_322mhz_axi_crossbar_synth_1, synth_1..…
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The source code [host.cpp](https://github.com/Xilinx/Vitis-Tutorials/blob/2023.1/Getting_Started/Vitis/example/src/host.cpp) for the host program of Vitis getting started tutorial calls `std::memcmp` …
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I built the perf_host design for U280. I could generate the bitstream, program the alveo, and load the driver. However, I got the following error when I tried to run the sw executable.
Number of re…
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Hi Mario,
I've been trying to compile a design on Alveo U280 based on "benchmark". As the design grew bigger, timing became an issue. I reduced the frequency of user logic following issue #42 to 1…
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I can't build the HW emulation. This error log is from running the code from this repo on a NERC VNC terminal:
```
make all TARGET=hw_emu DEVICE=/opt/xilinx/platforms/xilinx_u280_xdma_201920_3…
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I build the source files for this tutorial (01-rtl_kernel_workflow) for board alveo u280 and when i run i get this issue:
terminate called after throwing an instance of 'std::bad_alloc'
what(): s…
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Hi!
I built the code without modification from the main repo with switches:
vivado -mode tcl -source build.tcl -tclargs -board au200 -num_phys_func 2 -num_cmac_port 2
Then implemented the proje…
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Hello @nickfraser,
I have tried using this co-desidned framework for my project and was very helpful and informative. Now I can able to run synthesis using logicnets with the help of invoking vivad…