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Hello,
I'm currently trying to compile the bit stream for arty a7 35t fpga in the Linux-on-litex-vexriscv project from enjoy digital.
Here is the link for this project: https://github.com/litex…
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I get this error during compilation, I'm not quite sure what it means. Am I incorrectly initializing the entity?
Also, I'm trying to use my Altera DE0_CV as a slave device to talk to an Arduino Mas…
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Hi @tcal-x and @mithro ,
I was trying to change certain parameters of the d-cache on the Vexriscv using the scala file ([](https://github.com/google/CFU-Playground/blob/main/soc/vexriscv/src/main/scal…
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When trying to boot Rocketchip from the sdcard on the stlv-7325 board I get stuck on lift-off.
Using Vexriscv and the stlv-7325 board I can get sdcardboot to work at 100Mhz (with l2 disabled).
Using…
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The SymbiFlow project is slowly getting pretty decent support for the Xilinx Artix 7 part and more specifically the Digilent Arty A7 board. It would be awesome to have a SaxonSoC design in the [SymbiF…
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I cannot see the files referenced in readme the zip file that is downloaded from the relase page.
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If this addressed by a PR in flight, just close this.
I'm going through the examples at https://symbiflow-examples.readthedocs.io/en/latest/building-examples.html .
After the counter example is …
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The debug spec provides for an idle count to be used after every dm access.
This is read into info->dtmcontrol_idle.
This is never used; it presumably should be a baseline for idle_count in risc…
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First, we thank you for your impressive work. We would like to reproduce your work on our Artix A7 board.
However, we are not able to do reproduce it as we are getting the below error. Can you pleas…
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Hi,
- I met below error info when I tried to make prog in template proj. May I get help, thanks.
- I also plan to run it on XC7Z010-1CLG400C, so is there any reference guide for me ? Thanks.
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