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```
make -f Makefile.kv260 load
```
Everything goes fine until LiteX Python script execution :
```
poetry run python lib/litex-boards/litex_boards/targets/xilinx_kv260.py
INFO:SoC: __ …
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It is fairly difficult for me to verify the RTL for the CSR instruction against the Sail, since they are not really that related at the moment. I have done so, but it requires that I change a fairly l…
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### Should this be an RFC?
- [x] This is not a substantial change
### Which package is this a feature request for?
Other/unknown (please mention in description)
### Description
There are some cas…
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How can we implement this function? We need to read it from the SI5351?
dmd17 updated
2 weeks ago
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Corporate concern should be considered
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### Describe the bug
The collection transformer FastSFA has the option to return a scipy.csr_sparse.csr_matrix sparse representation of the dictionary. If this is done, the test fails, see
https:/…
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'The CLIC registers accessed via the indirect CSR mechanism don't belong to a particular mode (M or S). Instead, they exist outside the scope of any particular mode but are accessed via different indi…
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## Hello!
- Vote on this issue by adding a 👍 reaction
- If you want to implement this feature, comment to let us know (we'll work with you on design, scheduling, etc.)
## Issue details
Sim…
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1. Table 2 and Table 5 is both the mtype register layout, why show the layout twice?
2. in page 14, msettilek rd, rs1 # rd = new mtilek, rs1 = ATN, this is surely wong!
3. the deference and relation…
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update CSR_MINTSTATUS, CSR_SINTSTATUS, CSR_UINTSTATUS addresses to read-only csr addresses and add CSR_MINTTHRESH, CSR_SINTTHRESH, CSR_UINTTHRESH csrs.
spec: https://github.com/riscv/riscv-fast-int…