-
-
I read mixed signals [1] [2] to which extent we can access the Performance Monitoring Unit by using the `perf` command. I cloned and compiled the perf tool present in https://github.com/microsoft/WSL2…
-
Dear dCache Team,
We have tested a basic gplazma configuration with OIDC and LDAP [1]. The OIDC related properties consist of just 2 lines [2] and the connection to LDAP has also worked, where the …
-
I'm reading dcache source code to understand the cache coherence implemented by Tilelink bus, but the dcache code has almost no annotation with it. So is there any documents about dcache code ?
-
we may need to have another parameter for rucio servers which are not for general use
but are up and running, such as NERSC, FNAL_DCACHE_STAGING, etc.
https://docs.google.com/document/d/1lGKAM7LUeZ…
-
Hi,
I am having an issue with Vivado implementing a large number of BRAMs in the DCache. It appears that each byte in the cache is being implemented as an RTL RAM and then replaced with a BRAM for …
-
Hi, I notice that in the smp branch, the VexRiscv supports larger memory data width (e.g., 128 bits) which is bigger than the cpu data width (32 bits). However, in that branch, the cpu_dBus_cmd_payloa…
-
Hey.
it came up during the workshop that dcache.org may provide a APT repo with the dCache packages,...
Let's use this ticket to collect ideas for this.
1) Software:
There are several software syste…
-
Each memory access in a HPTWalk needs to be potentially flushed if the PMA/P checkers
generate an access fault. Specially the store on UDPATE_PTE needs to check for access violation.
// I think …
-
Hi,
Im trying to build a smp soc using NaxRiscv. I can find similar work as Litex done with VexRiscv. But I noticed that NaxRiscv's DCache is the one of write-back .
How to get the DCache read/wri…