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It seems that the iverilog invocation doesn't allow for SystemVerilog support:
https://github.com/google/xls/blob/c330e64365e56439ab9496159aa8664c6cd5eb6a/xls/simulation/simulators/iverilog_simulator…
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I am using IceStudio version below on Mac OSX Sonoma 14.3 (couldn't not copy it as text for some reason).
The iverilog and vvp binaries are already included with the IceStudio installation but …
zapta updated
5 months ago
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To be compatible with Icarus Verilog v10_2 (toolchain-iverilog v1.2.0)
Related to https://github.com/FPGAwars/icestudio/issues/209
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As we start to see more and more integration tests that require an IEEE simulator to run, it might make sense to add one to the CI. While proprietary simulators might be a pain to set up, we could sta…
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> **Describe the bug**
OpenFPGA fabric verilog configured with a bitstream has undefined outputs. This is true even for the and2 basic example provided in the template tasks/fabric_verification_templ…
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Hi,
this verilog code assigning the same wire to two different ports with different direction through two levels of hierarchy triggers an assertion failure.
```verilog
module a ();
wire aw;
…
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### Environment:
Icarus Verilog : 10.1(stable)
MyHDL : 0.10
Make: i686-pc-mingw32 (mingw32-make)
OS: windows7-64bit
### First Try:
Just type 'make' as "README" said.
Cause errors as bellow:
…
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Hi,
On my platform (macOS Sierra 10.12.5, vvp 11.0, iverilog 11.0) the display=True option of simulation.run doesn't provide realtime output when using the iverilog simulator. The simulation runs,…
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File example: https://afiskon.ru/s/20/502005b771_hello.vcd.txt
sump2.py crashes with following errors:
```
vcdfile2signal_list() : Parsing VCD Symbol Definitions
top_module is hello_sim
1000…
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Verification has failed on main branch:
```
$ make test
iverilog -o test.out src/*.v tests/programcounter_tb.v; vvp ./test.out; rm test.out
src/controller.v:327: warning: Extra digits given for …