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What model describes MOSFET behaviour using a "beta" and a fixed threshold? The few CMOS design textbooks' introductory chapters I looked at always model threshold as a function of the channel dimensi…
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How do you intend ground isolation to work? Is there another option other than shorting pins 2&3 on J15?
I can see the need to isolate everything on the "diode" side of the opto-isolators from the…
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Write a program in any provable language (Circom, Cairo, Noir, Rust) to provide a proof of K signatures out of N in a multisig setup.
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Hi mate, your library seams fantastic, I was looking for something that hardware-directly drives the power stage, leaving CPU for other purposes. I'm going to test it soon :) thanks for sharing!
As d…
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While we're migrating `mantle` into the core, we have an opportunity to revisit our design for the FPGA specific mantle targets.
# Primitives
Magma/mantle offer a set of primitives that can be use…
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Hosting Request
- Hosting Unit(Lab) Name: Digital Logic Design Lab
- Repository URL: https://github.com/virtual-labs/digital-logic-design-iiith
- Branch/Tag :[ master/v1.1.3](https://github.com/v…
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Edit timescale and signal sequences.
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## *Repository Creation Request*
Use this to get your experiment repository created or updated on GitHub under Virtual Labs organization.
1. #### Coordinating Institute:IIITH
2. #### Approver’s…
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Hi..
Three questions ..
First, does the program generate logic circuits?
second, does it generate a circuit from a file?
Third, Does it work by command line?
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### Is your feature request related to a problem? Please describe.
Ive ran into a problem. when trying to make complex binary logic you need a few simple things, gates, latches, and flip flops. Yes t…