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When converting a design to Verilog, a non driven signal is declared as ```wire```.
Sometimes, it should be declared as ```reg```. Typically, when instantiating a ROM.
## System information
```
…
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Just copy the conversion example from
http://docs.myhdl.org/en/stable/manual/conversion_examples.html
The "A small combinatorial design" example raised an exception.
I was using Python 3.6 on WIN1…
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VHDL is poorly supported by the open source toolchains. Verilog is much better supported.
It would be really awesome if this core was in Verilog instead of VHDL :-P
Then lots of the DisplayPort …
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I wrote down two files: Convolution_2x2.py (module), tb_Convolution_2x2.py (testbench)
I want to do below four things in one code **when I execute my testbench code (e.g. Command: python tb_Convolu…
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Converting a block to Verilog that takes a TristateSignal does not work if you also set 'initial_values=True'. The resulting error:
n = None, radix = ''
def _intRepr(n, radix=''):
…
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To be useful to me I need to be able to output to SystemVerilog instead of Verilog. I've added support for SV here: https://github.com/dj-on-github/myhdl which is working with basic examples but needs…
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I have the following function:
b1 = Signal(intbv()[8:])
b2 = Signal(intbv()[8:])
…
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## Steps to reproduce the issue
Python [http://www.myhdl.org](url) produce code like the example below.
```
module disa_test (a, b, oo);
input a, b;
output oo;
reg c;
always @…
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**Goal** Minimize the open issues in the Issue Tracker.
- Pick an issue you would like to fix. Check if it really refers to an issue, and suggest how to deal with it otherwise.
- Decide whether it is …
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I release this is probably a trackable issue.
Work that needs to be done to enable myhdl PyPi release from github
- [x] Get PYPI_API_TOKEN from PyPi
- [x] Setup github actions for release
- [ …