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Hello, excuse me,
I would like to ask what the "riscv_tracer" module is used for, and which stage of the processor pipeline does it work, how can I use it?
Can I use it to keep track of instruction…
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I'm trying to understand how Rocket-chip uses riscv-tests to test instruction sets and then uses it to my own processor.
how rocket-chip know the test result through these two macro. I'm confused abo…
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I'm trying to get a layout of the picorv32 riscV processor drawn.
It works! (with increased node stack size!).
However, the output image is very long and thin. 8000x31000px.
Is there a way to spe…
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I am trying to cause an overflow in 32 bit architecture. Writing to the lower 32 bit csr register mhpmcounter3 works; however; whenever I write to the mhpmcounter3h register, the value stays at 0. Eve…
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If you are interrested in contributing to the project, please let me know ^^
Here are the current work-items in completion order
- [x] Plugin API
- [x] Pipeline API
- [x] Basic frontend
- [x]…
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
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I noticed that, while `CSR_TIME` and `CSR_STIME` are [redirected](https://github.com/riscv/riscv-isa-sim/blob/master/riscv/processor.cc#L425) to `CSR_MTIME`, `CSR_MTIME` is [not implemented](https://g…
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Hi there,
Spike is actually a great functional model for riscv processor starter, but I found that there is no windows support for it, any plan to add support for windows?
If we have windows suppo…
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