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SpinalHDL
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VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger
MIT License
63
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7
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reset-vector issue
#19
zjin8520
opened
21 hours ago
1
RVF+cacheless LSU?
#18
Jzjerry
opened
5 days ago
1
Ieee 754 floating point -> Just a gentle question: Is there any plan to integrate the floating-point operations from the VexiiRiscv project into the SpinalHDL library?
#17
dreamflyings
opened
1 week ago
1
address width for xlen=64
#16
zjin8520
closed
1 week ago
4
Will VexiiRiscv be extended to support configuratble multi-issue ?
#15
franktaTian
opened
1 month ago
7
Shallower Pipeline for VexiiRiscv?
#14
Jzjerry
opened
1 month ago
1
How to blackbox `tilelink.fabric.RamFiber` in MicroSoc?
#13
Jzjerry
closed
2 months ago
2
Vexiiriscv instructions
#12
ztachip
opened
2 months ago
4
Bitmanip
#11
andreasWallner
closed
2 months ago
4
JNI error
#10
nachiket
opened
3 months ago
10
Run a simple bare metal program?
#9
nachiket
opened
3 months ago
1
Dev divradix2
#8
bitpasta
closed
4 months ago
4
Fix warnings
#7
typingArtist
closed
5 months ago
1
『Help』The features that can be used on naxriscv are not available on the vexiiriscv framework
#6
dreamflyings
closed
5 months ago
7
**Phenomenon** VexiiRiscv cannot be composed into new Module
#5
dreamflyings
closed
5 months ago
1
Add iterative shifter
#4
andreasWallner
closed
4 months ago
1
Fix random sim fails, add assert messages
#3
andreasWallner
closed
6 months ago
1
BuildBefore bug in plugin framework
#2
dreamflyings
closed
6 months ago
6
Roadmap / Contributing
#1
Dolu1990
opened
7 months ago
10