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In the base ISA, rv32i, we allow sll to accept either a register or an immediate as the shift count. sll with an immediate shift count is an alias for slli. It was suggested that for consistency, we…
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Should compiler expand "p" to {"zpn", "zpsfoperand"} or {"zpn"} on rv32 (e.g. in compiler)?
I.e. if I implemented Zpsfoperand, should I compile my code with `rv32gpzpsfoperand` or `rv32gp` is enough?
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The command to generate floating point assembly tests in the fadd.d_b1-01.S file[https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv32i_m/D/src/fadd.d_b1-01.S](https://githu…
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Should the RV32E ABI be explicitly targeted using `-mabi=ilp32e`? This would seem consistent with the other supported ABIs having unique `-mabi` strings. Of course for RV32E, no other ABI string is va…
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_This issue was automatically created by [Allstar](https://github.com/ossf/allstar/)._
**Security Policy Violation**
Project is out of compliance with Binary Artifacts policy: binaries present in sou…
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### Please describe the feature you'd like to see added.
Support the risczero platfrom by riscv32-unknown-elf-g++. which will bring more prove system for bitcoin.
### Is your feature related to a …
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LLVM differs from GCC in its support of the D extension when using -mabi=ilp32e.
Godbolt: https://godbolt.org/z/En7r85Gex
Assert: https://github.com/llvm/llvm-project/blob/069e8bcd82c4420239f95c7e6a…
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It seems that [this folder](https://github.com/riscv-ovpsim/imperas-riscv-tests/tree/v20221017/riscv-test-suite/rv32i_m/F) doesn't contain any `.S` files. Any ideas? Thanks!
For comparison, the f…
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The examples shown for the LA and LI insructions only work for RV32.
For RV64, any address at an offset of > +/-2GB won't work with the example shown.
The LI case has the same issue, as does the abs…
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The problem occurs for the assembly code generated by riscv-dv generator. The code generated y riscv-dv is assembled with gcc toolchain compiler:
`riscv64-unknown-elf-gcc -static -mcmodel=medany -fvi…