-
I am currently aiming to tape out a chip using SMIC's 180nm process. I am keeping the ibex core unchanged, but I need to embed SRAM on the chip. I use SMIC's memory compiler to generate the RAM's Veri…
-
What curious if the team would consider directly supporting a `pre-commit` hook based on https://pre-commit.com/#creating-new-hooks ?
-
Hi,
Thank you for the great library!
I want to use multi-dimensional input and output arrays in the setup [without reshaping to 1-D].
For this, I'm using system verilog instead of verilog, …
-
When building an FPGA image the tool analyzes verilog modules to determine if build depends on them,
A module can be declared with the beginning parenthesis on the first line:
module verilog_module …
-
Currently, we have a couple of purely structural Verilog files in OpTiMSoC: the toplevel files at various levels of the hierarchy. Creating these files is tedious and error-prone (getting wiring wrong…
-
Hello all,
I have followed the steps in the wiki:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/822312999/Building+and+Running+QEMU+from+Source+Code
`../configure --target-list="aarch64…
-
Environments
```
operating system WSL Ubuntu 20.04
cocotb version 1.8.1 (installed from pip)
verilator version 5.023 devel rev v5.020-176-g953249aa4 (built from source)
python version 3.10.14…
-
We are at the verge of reaching 50,000 downloads in the marketplace. From this point, I feel it is good to have a structured development plan. The following are a few ideas that I have.
## 1. Suppo…
-
The list of languages that Pieces supports is hidden away in the FAQ section of the website. It would be good to have them listed somewhere in the docs - where they would go is pretty ambiguous. My re…
-
Would it be possible to have rust-hdl output to circt. https://circt.llvm.org/
One could then use the LLVM/MLIR to optimize the output before outputting System Verilog or VHDL.
For example rust is …