CospanDesign nysa issues - Githubissues

CospanDesign / nysa

FPGA Development toolset

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README.md: little improvement to see titles correctly

#8 Martoni closed 7 years ago
1
modules generated with coregen are ignored

#7 cospan opened 9 years ago
0
valid verilog module syntax is not recognized

#6 cospan opened 9 years ago
1
Add a Stepper Motor Core

#5 cospan closed 10 years ago
1
Logic Analyzer Signals from the FPGA itself

#4 cospan opened 10 years ago
0
Logic Analyzer data data from the core doesn't start at the same position each time

#3 cospan closed 10 years ago
1
Logic Analyzer bits 29 - 31 are incorrectly pushed into lower bits

#2 cospan closed 8 years ago
0
Contiguous Memory incorrectly addressed in memory interconnect

#1 cospan closed 9 years ago
1