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- [ ] in the Bluespec simulator and
- [ ] via the Verilator backend build
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I think I made a really poor assumption several months ago that I'm hoping someone with mixed signal design experience can clarify. If you have a digital top and you want to add in, say, an ADC black …
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It can be useful to help the users simulate fault injections:
Implementation examples by Dolu1990 (via the Matrix channel)
```scala
def simBypass(that : UInt) = new Area{
val bypassEnabl…
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There are multiple cases of simulators calling a registered **VPI** callback while cocotb is still inside a previous callback.
This causes `to_python()` to log an error and `exit(1)`.
- **icar…
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Including the file [bsg_dff_chain.sv](https://github.com/bespoke-silicon-group/basejump_stl/blob/master/bsg_misc/bsg_dff_chain.sv) from BaseJump STL in a Lakeroad integration test can cause it to fail…
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I'm trying to use configs for some test bench:
> config tb_cfg;
> // Define top
> design tb_lib.tb;
> /* rules begin */
> default liblist lib1 lib2;
> /* rules end */
> endconf…
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Hello Serge,
You have done great work in this project. I really appreciate it. However, I am now stuck in the simulation step of kc705 testbench. I followed these steps to simulate it. I have gone to…
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Following the issues in #2093 and discussion #1722, I think we need to introduce two new system tasks, whose names _don't_ overload builtin system tasks and whose purpose is to end the currently runni…
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**Task** General support for indexed constants.
**Description** http://dev.myhdl.org/tasks/indexed-constants.html
**Complexity estimation** This is probably a hard task. It has multiple facets, as i…
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In pull-request #2394 I made a comment about using `illegal_bins`. An illegal bin is excluded from coverage, but if the goal is to exclude bins it is best to use `ignore_bins`. When an illegal bin i…