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Right now, we are using a two-step setup for Synopsys VCS which according to http://www.vlsiip.com/vcs/ is limited to Verilog only. VCS(-MX) is capable of simulating VHDL too with a three-step process…
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Following the issues in #2093 and discussion #1722, I think we need to introduce two new system tasks, whose names _don't_ overload builtin system tasks and whose purpose is to end the currently runni…
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In pull-request #2394 I made a comment about using `illegal_bins`. An illegal bin is excluded from coverage, but if the goal is to exclude bins it is best to use `ignore_bins`. When an illegal bin i…
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**Task** General support for indexed constants.
**Description** http://dev.myhdl.org/tasks/indexed-constants.html
**Complexity estimation** This is probably a hard task. It has multiple facets, as i…
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**Is your feature request related to a problem? Please describe.**
I am currently working on implementing the [RVVI](https://github.com/riscv-verification/RVVI/blob/main/source/host/rvvi/rvvi-trace.s…
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The test generation flow appears broken when I try to customize the default target rv64gc with PMP support for SV39 mode on Mentor or Cadence simulators?
I've pulled in upstreams upto `d74484b -…
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Hello,
I am trying to obtain the VCD file from an execution of a the hello example code in the Simple Runtime using the Ibex (formely zero-riscy) core.
I run my code using `make run vsim/script=…
Merok updated
3 years ago
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Hello, I discovered another issue with functions when submitting #980. I couldn't find anything in the 1800-2017 spec about this specific issue, but I assume my proposed changes will help `iverilog` m…
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Spinal version: v1.10.1
Simulation tool: Synopsys VCS 2018
Here's the simulation code:
```scala
SimTimeout(500 ms)
val perpPort = dut.socInst.logicMainInst.coreInst.io.d_perp
…
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1. Add `stop(code: UInt): Unit`. I am not sure whether it is possible. It could be more useful if `stop` can pass the internal circuit state outside.
2. Add `finish()`, finish has different meanings …