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### Version
Yosys 0.30+48
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
I have come across an inconsistency problem during the synthesis process while using Y…
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BSC can generate a Verilog simulation for a design, using the `bsc_build_vsim_*` scripts in `src/exec/`. These scripts run the Verilog tool (iverilog, Questa, etc) to generate a simulation binary, an…
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OpenVAF currently does not recognize the multiplicity attribute. This attribute has no impact on the actual simulation.
It is only used to scale operating variables by `$mfactor` when reported to the…
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Bluesim self-checking testbenches using `dynamicAssert` wind up exiting with status 0 whether they pass or fail. This makes them difficult to integrate into conventional test frameworks (or, for that …
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For testing with netlists I need some vendor libraries. These are shipped with the simulator ActiveHDL and I use this to include them
```
vu.add_external_library('pmi_work', activehdl_lattice_path /…
ghost updated
4 years ago
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### Problem
The specific issue I am having is that fsdb dumping cannot be done if Verdi is not installed or linked to VCS. I am running VCS (S-2021.09) on university computers with DVE addon.
Th…
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## Steps to reproduce the issue
Synthesize e.g.:
```
function void read_next_instr([31:0] _next_pc);
endfunction
```
## Expected behavior
Will synthesize ok. e.g. verilator and …
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I used the default configuration of Gemmini and, after generating files in Verilator, I intended to execute resnet-pk on this simulator. However, the following error occurred. What should I do?
`…
GGKOP updated
4 months ago
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Hi,
While debugging a libcocotbvhpi.dll missing issue for cocotb1.3, I noticed that some parts of the Makefile.aldec is incomplete. Like the below:
```
else ifeq ($(TOPLEVEL_LANG),vhdl)
```
is …
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For a particular use case see mor1kx-generic:
https://github.com/stffrdhrn/mor1kx-generic/blob/master/mor1kx-generic.core#L61
For verilator there is a build stage which needs parameters like `--pi…