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### Version
Yosys 0.45+106
### On which OS did this happen?
Linux
### Reproduction Steps
See attached archive. It contains the input verilog file, the Makefile, and the log of last Yosys run.
Ju…
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Hi, everyone!
I'm trying to build finn_examples network resnet50_w1a2 but I'm getting:
`ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:hls:Pool_hls_1:1.0`
As shown in the build …
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I’m setting up my environment and trying to get my VCK5000 to work, but I’m encountering quite a few issues. My current question is, according to the website, I should install the global version of RO…
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## troubleshooting
### Xilinx JTAG Programmer (USB) cable not found
> [!IMPORTANT]
> ***Only Platform Cable USB II
Platform Cable USB Model: DLC9G is supported!!!!!!!!!!!!***
> ~~do not use digi…
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Hi there,
I'm trying to compile an updated version of ffmpeg that support .exr DWAA encoding for AWS's VT1 instances. I've run through the [ffmpeg compilation docs](https://trac.ffmpeg.org/wiki/Co…
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Hello, World!
We are a group intending to accelerate some Pytorch operations on Xilinx UltraScale FPGAs. However, we are a little lost to where to begin to port the functions.
From what we could…
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Block RAMs can be inferred using either the correct coding style or Xilinx Parameterized Macros (XPM) such as used in the `tc_sram`s.
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I am not sure what I should set XILINX_BOARD to ? I am using a zybo whose part number is xc7z010clg400-1
since I didn't find the XILINX_BOARD value for my board I just kept the default one ( em.avne…
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## Issue Description
`memory_libmap` pass in Yosys 0.18 and newer would synthesize LUTRAMs unsupported by nextpnr including:
- RAMS32 (manually instantiated)
- RAMD32 (manually instantiated)
- R…
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```
make -f Makefile.kv260 load
```
Everything goes fine until LiteX Python script execution :
```
poetry run python lib/litex-boards/litex_boards/targets/xilinx_kv260.py
INFO:SoC: __ …