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Dear,
This is the error I am encountering while make process.
I checked everything and think all are fine. But could find out the exact reseason for this
make
g++ -Wall -O2 -g -MMD -I /usr/local…
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On which board this code is targeted.........?
ultrascale zynq or only zynq..........?
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Hi,
I downloaded this pre-built and put it on a SD card, and insert the card into ZYBO board. Once I connect the board via the serial port and open a terminal (putty), I can see the "PetaLinux" log…
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LK"I
Hi ,
Is this repository supports ZCUxx chips?
like you described here (just replace the Zynq base release with 2018.1-zcu106-release.tar.xz :
[https://www.digikey.com/eewiki/display/li…
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Hi it seems the changes needed for 2021-2023 is minor.
```
diff --git a/examples/alpha250/adc-dac-dma/block_design.tcl b/examples/alpha250/adc-dac-dma/block_design.tcl
index e28f2090..edb64099 10…
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Platform defining:
Take LiteX -> Read run instruction -> build ready-design for Arty board (using arty.py) -> try to build it on Zynq -> copy Arty definition and arrange it for our board* (don't forg…
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Hi, David. I am interested in you zynqnet. It's really a great work. Thanks for sharing. I learnt a lot from you report and code. So I am trying to test you CNN on my own ZedBoard these days and have …
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It appears we don't have any examples / demos which run on Zynq parts at the moment?
I don't know which board should be targeted?
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INFO: Fetching U-Boot
+git submodule init xilinx-uboot
+git submodule update --remote --depth 1 xilinx-uboot
+git fetch --depth 1 origin master
+git checkout FETCH_HEAD
Target U-Boot fetched
INF…
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I'm looking at adding some support for ACE 4 on top of the `amba4.axi` classes we already have in `spinal.lib`, but I'm not super sure on what's the best way to proceed here. ACE adds two extra chann…