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To raise-awareness and lower the barrier to testing Verible, should we push to deploy at edaplayground.com or consider our own playground? @mithro WDYT?
When we were brainstorming project ideas, h…
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These aren't allowed by the Google style guide. Pointed out by @mcy in a recent review.
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**Type of issue**: other enhancement
**Impact**: no functional change
**Development Phase**: request
**Other information**
**What is the current behavior?**
Currently, a…
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Hi guys,
I tried to synthesize pulpissimo down to gate-level using Synopsys Design Compiler (I used gtech.db as target library for test purposes). The synthesis basically worked (except of course t…
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### Version
Yosys 0.29+11 (git sha1 acfdc5cc4246 gcc 9.4.0-1ubuntu1~20.04.1 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
Hi there!
I noticed that for one …
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We currently have two ops that behave differently (and are interpreted/handled differently), `sv.reg` and `sv.logic`.
Both claim to "Declare a SystemVerilog Variable Declaration of 'reg' type." (or…
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**Describe the bug**
In the following code, the `Width` parameter, which should be set to `8`, is incorrectly computed as `-1` by slang. This discrepancy only occurs under certain conditions involv…
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Our simulator makefiles get the list of Verilog and VHDL sources in separate variables, and in ``Makefile.questa``, ``Makefile.aldec``, ``Makefile.activehdl``, there are separate compiler calls to com…
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Bluesim self-checking testbenches using `dynamicAssert` wind up exiting with status 0 whether they pass or fail. This makes them difficult to integrate into conventional test frameworks (or, for that …
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Hello!
I'm currently writing a firrtl lexer/parser for yosys using flex/bison and am a bit stuck because
the grammar of firrtl is not context-free.
This is because firrtl allows an id to be a res…