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It would be great if there was one unified way to write faster python extensions. For various reasons we can't really port cython to micropython, but what aboutproviding some way for cpython to run mp…
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The goal is to both:
* Make it easier for all people discovering SpinalHDL (knowing VHDL and Verilog might help but it is not a requirement)
* Make it easier for people to find information
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### Enhancement Description
- One-line enhancement description: dynamic resource allocation
- Kubernetes Enhancement Proposal: https://github.com/kubernetes/enhancements/tree/master/keps/sig-node/…
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[ **autistic.sack.of.friends** on Discord says](https://discord.com/channels/890222432605057044/1196224123018412184/1196224123018412184)
> this one looks potentially useful:
https://modrinth.com/mod/…
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Hi everyone, I would like to write a small tool which, given a VHDL file describing an entity plus its architecture, would allow me to draw its corresponding schematic. It should at least include:
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commit: 7201a1d
Schematic review only.
# Review sethkaz:
### Fix:
- I might be wrong on this, but I believe the power ORing circuit might not work as intended.
- I believe the diodes shoul…
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Right now connectors implement certain types of behavior that could be reused. The most common example is filtering groups.
Consider creating a common middleware layer for connectors instead of imp…
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**Is your feature request related to a use case or problem? Please describe.**
The operation $e^{i \theta P}$ where $P$ is a pauli string, appears a lot in discussions around rotations and magic stat…
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**Is your feature request related to a problem? Please describe.**
Bitwise calculations are very crucial in competitive programming, Logic gates, Computer Architecture, Electronics engineering, mathe…
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### Is there an existing issue for this?
- [X] I have searched the existing issues
### Version
higher than v1.15.7 and lower than v1.16.0
### What happened?
While installing Cilium with…