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Hi all,
I am new to Pulpino. I installed the software and run the helloworld program and the output is displayed
in vsim console. Thats fine.
I did not understand how the hello world is transmi…
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Hi Mr. Pavel,
I'm trying now to read some analog values using the IP XADC Wizard.
For hardware configuration, I used the TCL code you implemented.
```
cell xilinx.com:ip:xadc_wiz:3.3 xadc_0 {
…
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I've been thinking long about having some multiplatform (windows and gnu/linux), free (libre), lightweight and standalone tool to analize large bodies of VHDL 2008 code at block/RTL level. That tool w…
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HI Designer,
I could see below line of commented text just above adv_dbg_if instantiation in "core_region.sv" module.
// TODO: remove the debug connections to the core
Q1. What does it …
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I have downloaded RTG4_CoreRISCV_AXI4_BaseDesign. Libero complains that the core AXI_GLUE_LOGIC is missing. See the following error:
Reading file 'bfm_main.v'.
Reading file 'reset_synchronizer.v'.…
ghost updated
7 years ago
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ghdl -v:
```
GHDL 0.34 (2017-03-01-203-g06a78d22) [Dunoon edition]
Compiled with GNAT Version: 7.2.0
GCC back-end code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2015 Tristan…
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Dear Pavel,
I saw the Matlab example. It is very clear, a very good educational tool. However, I would like to know more about the hardware configuration.
1. I can understand that the Redpitaya …
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In GitLab by @daniel-k on Feb 13, 2018, 14:30
_Merges feature/memory-manager -> develop_
This MR implements a global memory graph of memory mappings between address spaces. The graph can be traverse…
stv0g updated
6 years ago
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Hi there!
I found out that this software (Scatter Gather mode) will not work properly if transfer data size more than 2^23 (8 Mb).
Yesterday I saw the sources and found out that in SG mode only o…
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What I really want is to produce Verilog from a LazyModule without knowning its IO bundles.
For what I understand, the current GeneratorApp accepts Module, rather than LazyModule. Therefore, I need…