-
The [test_vectors](https://github.com/lowRISC/opentitan/tree/master/hw/dv/sv/test_vectors) area currently cater to SHA256, HMAC, SHAKE and KMAC vectors from NIST. For AES, a separate solution is being…
-
I first discovered the issue with Clash version 1.4.7 but it seems to still be around with the version of clash documented on `https://clash-lang.org/install/linux/` (stackage lts-19)
Small repro c…
-
Symbols get added to the symbol cache in `gatherFiles` ([specifically this `TypeSwitch`](https://github.com/llvm/circt/blob/d2e29b53634ca64d66c1d32f57210f4ec40d0fe5/lib/Conversion/ExportVerilog/Export…
-
This issue is used to announce breaking changes (and possibly other critical info). Users are strongly encouraged to subscribe to this issue to get notified of such changes.
Every breaking change i…
-
riscv-dv initializes floating point CSRs frm using init_floating_point_gpr(). I want to add randomization to certain CSRs in the main function without breaking the existing setup. Kindly suggest any w…
-
Hello, I discovered another issue with functions when submitting #980. I couldn't find anything in the 1800-2017 spec about this specific issue, but I assume my proposed changes will help `iverilog` m…
-
### 岗位ID
2
### 对岗位的认知
### 1、自身优势
**本人性格开朗、做事稳重，有着积极进取的精神及良好的分析判断能力。能迅速适应各种环境并融入其中。有较强的责任心，能和同事建立好有效的沟通。工作风格严谨、积极，注重细节，具有较好的独立学习能力，有能力快速掌握新知识和技能，并将其应用于实际情境中。此外，有较强的自我管理能力，能够管理自己的时间和资源，保持高效和专注，从而达成…
-
Add the logic type `lN`, e.g. `l32` or `l9001` which represents a IEEE 1164 value, i.e. `UX01ZWLH-`. Decide whether to allow for arithmetic to occur on logic types, or if a conversion function should …
-
## Issue
It recently came up in the RISC-V meeting that the bitfield syntax is limited when we want bitfields with fields that can vary in width depending on XLEN, or the virtual memory translation…
-
Currently, the workflow for the tutorial page is:
1. someone edits `tutorial.v`
2. when Jade next wants to edit the tutorial, she regenerates the HTML using her locally installed Alectryon (what ver…