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### 🎮 Game Request
Game logic and basic description
Quantum Maze" that involves navigating through a maze with quantum mechanics principles, including superposition and entanglement.
### Point down…
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Hello!
First of all, thank you for this amazing Wired-Redstone mod! It adds very useful redstone components like logic gates and data buses.
I have a few suggestions on what could be added in futu…
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Hi there, not an issue more of a question.
Currently for formal verification SymbiYosys and Verilog/SystemVerilog are used. As documented [here](https://spinalhdl.github.io/SpinalDoc-RTD/master/Spi…
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# Story
As UCSD, so that I can ingest an NBS result message, I need observations provided by CDPH to use codes that I support.
## Pre-conditions
- We've identified a list of observation codes use…
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As the title says, there is a great possibility that the application-specific `Operator` would leverage `PVC`'s `Annotation` for storing custom data. The custom data will tell storage provisioner how …
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www.aqdi.com/wordpress/PCBChecklistLive.htm
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I found this mod by accident and it is the perfect Redstone upgrade. I'm a programmer, so I think in code better than Redstone, but I do like Redstone. I want to share builds and code with others who …
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*Issue migrated from trac ticket # 1279*
**component:** osd/core | **priority:** major
#### 2014-12-23 04:52:11: @jandegr created the issue
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> Below a few samples, causes and hopefully even sol…
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### Situation ###
Operator classes like `Matrix` or `MatrixSymbol` represent scalar results as multiple of their respective Identity operator, i.e. operator * operator -> operator (except for 0):
``…
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### Feature Description
Hi ,
I have a 8 bit adder RTL code for full adder. and my library contains a full adder cell.
But yosys is not able to map to the full adder cell which has output pins…