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When using system tasks like $display, bsc insert a couple of #0 delays. I'm not sure if they are useful for event based simulator, but when using verilator it generates errors because delays are not …
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Hello all!
I am trying to simulate ```cva6``` on ```vivado 2021.1``` and facing an error which is unknown to me. can anyone point out the source of the error. below is the elaboration log of the sim…
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I would like to request that an option be added to logic gates to set the number of inputs, similar to how SPDT switches have an option to set the number of throws. This would make some circuits simpl…
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I have installed cocotb using pip and all my environment variables are in correct position. When I try to run the command ```make SIM=icarus``` I get the error ```System cannot find the file specified…
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The attached simple switch.va got panick with v 22.12.0.
`dietmar@modsys:~/Projects$ RUST_BACKTRACE=1 openvaf -I .. switch.va
thread 'main' panicked at 'the parser seems stuck', openvaf/parser/src…
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```
========================================================================================== test session starts ====================================================================================…
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Cocotb has a simple test intended to show simulators can discover system verilog interfaces using this code: https://github.com/cocotb/cocotb/blob/master/tests/test_cases/test_sv_interface/top.sv
C…
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Many dozen of the Icarus Verilog tests run against Verilator in SV-Tests fail with this unsupported message
%Error-ZERODLY: ...: Unsupported: #0 delays do not schedule process resumption in th…
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It would be a nice feature to have the makefiles able to take in a list of directories that are part of the include list and not the source, and format them correctly for each tool. I am working betw…
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In generated file `__024root.h` we have multiple `CData` declaration that store data. Is it possible to access to information to which cell and pin they correspond at the simulation stage?
Since we c…