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In fpga-zynq we use a serial adapter/tether to write into the L2 of rocketchip.
When i mix the serial adapter traits into my cake i get an exception (below). The same error can also be exercised b…
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I'm using custom single core configuration without L1toL2interconnect:
*RocketTile TLToAXI4 AXI4 interconnect*
and I see the following wrong behavior (that probably will interest you):
…
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In this issue needed to determine the standard requirements and implementation of Double Data Rate on data serial of eMMC host controller
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Verilog has useful feature some people are used to using. It's an assignment signals concatenation to another signal.
In Verilog it look's like: `assign {a,b,c} = z; `
Chisel3 has a `Cat()` fun…
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during the process of converting the IP cores to full Vivado IP Catalog cores I found that at least some AXI IP cores have invalid-meaningless memory range settings the way they are created by the tcl…
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Howdy,
I'm trying to build the memcpy example for the KU3 with Vivado 2016.4, and am running into errors during the synthesis of 'psl_fpga'. Below is the results of my `make` attempt
```
$ make…
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Hello Pavel,
Thanks a lot for your very helpful work !
In your `sdr_transceiver` project, you use a Xilinx `FIFO generator` core in combination with two custom cores (`axi_axis_reader` and `axi_axis_…
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Pavel,
It seems that with the latest SW release of HPSDR transceiver CW is not working anymore.
When connecting the key to the dedicated pin of the RED PITAYA and putting HPSDR in CWU or CWL
ther…
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Hi,
I am currently trying to port the design to Vivado 2015.4, but it does not support the tpg 6.0 core. The new TPG core only has one clock input. What should I do?
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| | |
|--------------------|----|
| Bugzilla Link | [PR15640](https://bugs.llvm.org/show_bug.cgi?id=15640) |
| Status | RESOLVED FIXED |
| Importance | P…