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I'm currently working on a university project. But im struggling with adding my one device to the Chip.
For the project I need to get a pwm working, which is a nice coincidence.
Anyway with the cur…
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Hi;
in master branch, i followed instructions in readme.md, after build toolchain,
then in the emulator dir,
when i "make run", then it fails in any test.
in each *.out file like:
$ cat output…
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Hello,
I want to make verilog DefaultFPGAConfig and I get the following error. Could anyone please tell me why I'm getting this error ?
Also, I want to make verilog for the zedboard, should I use…
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I've been trying to instantiate dual-memory channel configurations, but I get Chisel elaboration errors. At first I get
java.lang.IllegalArgumentException: requirement failed: minAlignment (64)…
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build error while generate verilog for FPGA config.
paladinw@ubuntu:~/mine/riscv/rocket-chip/vsim$ make verilog CONFIG=DefaultFPGAConfig
mkdir -p /home/paladinw/mine/riscv/rocket-chip/vsim/generat…
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I run the command "make rocket" under fpga-zynq/zedboard.
When it run to the 40 line in the fpga-zynq/common/Makefrag :
make verilog MODEL=ZynqAdapter CONFIG=$(CONFIG); \
It will occur the error.…
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https://github.com/freechipsproject/rocket-chip/blob/9002e7e53299598027f41b95dba1666310923699/src/main/scala/rocketchip/DebugTransport.scala#L22
```scala
class JtagDTMKeyDefault extends JtagDTMCon…
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I am studying debug mechanism (JTAG with OpenOCD). I reference https://github.com/riscv/riscv-tests/tree/master/debug to figure out that. I haven't SiFive Board (e300, u500), so I want to try in Simul…
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I try to use `MultiClockCoreplex` at the current master branch (commit 549e006988). First, I have to modify code as below. Then I have to add extra I/O ports for different clock and reset input in the…
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I built `bbl` with an smp-enabled `vmlinux` as payload. It runs well under `spike -p2`. But when I ran it in a multicore rocket chip on zedboard through `./fesvr-zynq bbl`, it failed with such a log:
…