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Hello again! Still greatly enjoying my adventures with Clash :) I've recently stumbled across an issue that may simply be user error.
I have a simple function that takes in an ASCII BitVector and…
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Can you attach an example that shows the issue? (Must be openly licensed, ideally in test_regress format.)
I started chasing this down with an error in the statement:
wire [839:0] large;
…
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I've just installed cocotb and I am trying to run the first D Flip-Flop example from the official page (https://github.com/cocotb/cocotb/tree/master/examples/simple_dff) .
I've copied the verilog fi…
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First of all, thanks for putting together this great example for UPDuino projects, I appreciate the effort you've put in to share it!
I've clone the project and was stepping through the README and …
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Hi all,
With reference to #2028 it seems like, if I install `pytest` I'll get helpful assertion failure messages. I was getting a warning about `pytest` not being installed at first, and then I ins…
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I can create a component with the name `Accumulator (128 bits)`. However, this will be used directly in Verilog without escaping, and thus produce syntax errors. Either restrict `setDefinitionName` to…
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It seems I can write something like `m.d.comb += Assert(Past(signal) == 0)`. If `multiclock` is off in the sby file, what exactly is `Past`?
Here's an example. First, `example.py`:
```python
f…
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I just cloned a fresh thesdk_template v1.8 and the inverter simulation fails with the following output:
Click to expand
```
$ ./configure && make
Generating Makefile
cd /home/pro/a-core…
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I experience seg faults when running both my testbenches, and also with the examples in this repo with verilator 4.106
These occur somewhere within `vlog_startup_routines_bootstrap()`, in `verilato…
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Currently we don't have a wishbone slave implementation, which is required if we want to perform any memory accesses. I've researched our options with regards to fixing this and they're as follows (in…