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vivado.py function _read_compile_order() used by add_vivado_ip() fails with assertion when compile_order.txt contains references to files that are not VHDL or Verilog. However, some Vivado IP include …
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I am trying to simulate LetNet with the MNIST dataset.
OS: Ubuntu
Simulator: ModelSim
The simulator calls $finish with "DRC Error: Reset is unsuccessful at time 1237600. RST must be held high for…
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**What programming language should we add?**
SystemVerilog (less preferably -- Verilog)
**What is the official website for the language?**
There's no official website, but here are links to the …
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To verify 8- bit ALU using a reference model for comparison, I am facing issue with the assertion for the randomised test using ‘randint’ in a for loop, the problem being the control from Python TB to…
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### Is your feature request related to a problem? Please describe.
Recently, I'm developing for some FPGA using Verilog, which is a Hardware Description Language. Common setup for Verilog uses Makefi…
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The convergence behavior of HBTs with current biasing at the base is problematic, likely related to the $limit function that
is missing in Verilog-A models.
A minimum netlist is printed below fo…
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Hello,
Thanks for this great work, I appreciate the whole work. It is extremely beneficial.
Actually,I removed the constraint file of KC705 board, and I used the constraint file of VC707 board, and …
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Hi,
I want to ask a few questions about using hammer with the chipyard.
1. Is it possible to skip using asap 7 calibre deck to perform synthesis?
`make buildfile` needs the deck file.
*I use `…
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There's a problem when trying to run mixed language simulation under Aldec Riviera.
The problem can be reproduced even with the example in the repo.
Apart from the already known issue with VHDL->Ver…
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Does not appear to repro when extracted as a separate function which just takes the parameters as arguments (rather than embedded in an array of pointers). Might be something to do with the JIT envir…