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I am using V4.5 of the CEP and I cannot compile the chipyard as per the instructions:
make -f Makefile.chipyard
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Running w…
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## Describe the bug
jtop crashes after running for a while
## To Reproduce
Runs fine for a while. Time until failure is not deterministic. It happened twice after running for just a few minut…
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**Describe the bug**
Impossible to install
**To Reproduce**
```
sudo -H pip3 install --upgrade jetson-stats
[sudo] password for orin:
Collecting jetson-stats
Downloading jetson-stats-4.1.0…
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Xcelium/VHDL fails the test test_timing_triggers/test_readwrite_in_readonly as follows:
```
15119.00ns INFO cocotb.regression running test_readwrite_in_readonly (78/194)
…
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This compilation error seems to be related to initial blocks and loop unrolling. I have attached a verilog file that cause the compilation error.
[t.txt](https://github.com/verilator/verilator/file…
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Test for GHDL are failing. See: https://travis-ci.org/potentialventures/cocotb/jobs/507809192 #859
Same test pass in Questa.
First step is to add `GHDL_ARGS ?= --ieee=synopsys` to https://github.…
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This is a very specify issue that only occurs when manually editing the VVP source file, but an issue nonetheless.
For my work on SDF interconnect, I need to add input and output buffers to modules…
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I am compiling a SystemVerilog design using Verilator version `Verilator 5.014 2023-08-06 rev v5.014` on Ubuntu 22.04.
My design is made of few modules, with a top-level wrapper named `TOP` that in…
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I asked a question here https://github.com/ocaml/opam-repository/issues/23914, and I did a little google search, and I found this project and https://github.com/ujamjar/hardcaml-vpi is the most match …
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**Describe the bug**
Hello @rbonghi :)
I've been using jtop 4.1.5 on Xavier for a few days now and I have some kind of strange issues with jtop.service that forces me to restart the service once e…